SM CODE IIC_SM_1
Detailed implementation
I2C communication module embeds protocol error checks (like overrun, underrun, packet
error etc.) conceived to detect network-related abnormal conditions. These mechanisms are
able anyway to detect a marginal percentage of hardware random failures affecting the
module itself.
Error reporting Error flag raise and optional interrupt event generation
Fault detection time
Depends on peripheral configuration (for example baud rate). Refer to functional
documentation.
Addressed fault model Permanent/transient
Dependency on Device configuration None
Initialization Depends on implementation
Periodicity Continuous
Test for the diagnostic Not applicable
Multiple-fault protection IIC_SM_2: Information redundancy techniques on messages
Recommendations and known limitations
Adoption of SMBus option grants the activation of more efficient protocol-level hardware
checks such as CRC-8 packet protection.
Enabling related interrupt generation on the detection of errors is highly recommended.
Table 120. IIC_SM_2
SM CODE IIC_SM_2
Description Information redundancy techniques on messages
Ownership End user
Detailed implementation
This method is implemented adding to data packets transferred by I2C a redundancy check
(such as a CRC check, or similar one) with encoding capability. The checksum encoding
capability must be robust enough to guarantee at least 90% probability of detection for a
single bit flip in the data packet.
Consistency of data packet must be checked by Application software before consuming data.
Error reporting Depends on implementation
Fault detection time Depends on implementation
Addressed fault model Permanent/transient
Dependency on Device configuration None
Initialization Depends on implementation
Periodicity On demand
Test for the diagnostic Not applicable
Multiple-fault protection CPU_SM_0: Periodic core self-test software
Recommendations and known limitations
It is assumed that the remote I2C counterpart has an equivalent capability of performing the
check described.
To give an example on checksum encoding capability, using just a bit-by-bit addition is
unappropriated.
This method is superseded by IIC_SM_3 if hardware handled CRC insertion is possible.
Table 121. IIC_SM_3
SM CODE IIC_SM_3
Description CRC packet-level
Ownership ST
UM2305
Hardware and software diagnostics
UM2305 - Rev 10
page 68/110
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