Basic Configuration Options
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14
SLUUBD3D–September 2015–Revised September 2018
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Basic Measurement System
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Low Byte FTEMP CTEMP RSVD ExtAveEN VAUXEN VAUX_SCALE
IN_SYSTEM_
SLEEP
SLEEP
FTEMP (Bit 7): FET Temperature Protection Source
0 = Maximum of external available sources (default)
1 = Average of external available sources
CTEMP (Bit 6): Cell Temperature Protection Source
0 = Maximum of external available sources (default)
1 = Average of external available sources
RSVD (Bit 5): Reserved
ExtAveEN (Bit 4): Enables the bq78350-R1 to measure the BAT input
0 = BAT input is not measured.
1 = BAT input is measured and made available via ExtAveCellVoltage() (default).
VAUXEN (Bit 3): Enables the bq78350-R1 to measure the VAUX input
0 = VAUX input is not measured (default).
1 = VAUX input is measured and made available via VAUXVoltage().
VAUX_SCALE (Bit 2): Enables the bq78350-R1 to scale the VAUXVoltage() data by 10. For example:
Units are 10 mV rather than 1 mV.
0 = VAUXVoltage() is not scaled (resolution is 1 mV) (default).
1 = VAUXVoltage() is scaled (resolution is 10 mV).
IN_SYSTEM_SLEEP (Bit 1): IN SYSTEM SLEEP mode
1 = Enable
0 = Disable (default)
SLEEP (Bit 0): Enables the bq78350-R1 to enter SLEEP mode.
0 = The bq78350-R1 never enters SLEEP mode.
1 = The bq78350-R1 enters SLEEP mode under normal sleep entry criteria (default).
2.6.2 FET Options
This register configures the various FET control options.
Class Subclass Name Format
Size in
Bytes
Min Max Default Unit
Settings Configuration FET Options hex 2 0x0000 0xFFFF 0x0021 —
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
High Byte RSVD RSVD RSVD RSVD RSVD RSVD KEY_POL PCHG_POL
Low Byte RSVD SLEEPCHG CHGFET CHGIN CHGSU OTFET KEY_EN PCHG_EN
RSVD (Bits 7–2): Reserved
KEY_POL: This bit configures the KEYIN input detection polarity.
0 = KEYIN detection is active low (default).
1 = KEYIN detection is active high.
PCHG_POL: Configures the bq78350-R1 PRECHG pin output polarity. If PCHG_EN = 0, then this bit
has no influence.