Texas Instruments bq78350-R1

Charge and Discharge Alarms www.ti.com
50
SLUUBD3D–September 2015–Revised September 2018
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Charge Algorithm
15 14 13 12 11 10 9 8
RSVD RSVD RSVD SBS_COMP RSVD RSVD FCCLEARRSOC FCSETRSOC
7 6 5 4 3 2 1 0
FDCLEARRSOC FDSETRSOC TCSETVCT FCSETVCT TCCLEARRSOC TCSETRSOC TDCLEARRSOC TDSETRSOC
RSVD (Bits 15–13): Reserved
SMB_COMP (Bit 12): Enable SOC FLAG Smart Battery Standard specification compliance
1 = Enabled
0 = Disabled (default)
RSVD (Bits 11–10): Reserved
FCCLEARRSOC (Bit 9): Enable FC flag clear by RSOC threshold
1 = Enabled (default)
0 = Disabled
FCSETRSOC (Bit 8): Enable FC flag set by RSOC threshold
1 = Enabled
0 = Disabled (default)
FDCLEARRSOC (Bit 7): Enable TC flag set by primary charge
1 = Enabled (default)
0 = Disabled
FDSETRSOC (Bit 6): Enable FD flag set by RSOC threshold
1 = Enabled (default)
0 = Disabled
TCSETVCT (Bit 5): Enable TC flag set by primary charge
1 = Enabled (default)
0 = Disabled
FCSETVCT (Bit 4): Enable FC flag set by primary charge
1 = Enabled (default)
0 = Disabled
TCCLEARRSOC (Bit 3): Enable TC flag clear by RSOC threshold
1 = Enabled (default)
0 = Disabled
TCSETRSOC (Bit 2): Enable TC flag set by RSOC threshold
1 = Enabled
0 = Disabled (default)
TDCLEARRSOC (Bit 1): TDCLEARRSOC—Enable TD flag clear by RSOC threshold
1 = Enabled (default)
0 = Disabled
TDSETRSOC (Bit 0): TDSETRSOC—Enable TD flag set by RSOC threshold
1 = Enabled (default)
0 = Disabled