Texas Instruments TMS320F28069 - Page 103

Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master in data
must be valid
Master out data Is valid
1
7
6
10
3
2
SPISTE
(A)
103
TMS320F28069 , TMS320F28068 , TMS320F28067 , TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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Detailed DescriptionCopyright © 2010–2016, Texas Instruments Incorporated
A. In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-34. SPI Master Mode External Timing (Clock Phase = 1)