Texas Instruments TMS320F28069

XINT1, XINT2, XINT3
t
w(INT)
Interrupt Vector
t
d(INT)
Address bus
(internal)
78
TMS320F28069 , TMS320F28068 , TMS320F28067 , TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F –NOVEMBER 2010–REVISED MARCH 2016 www.ti.com
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Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated
6.8.1 External Interrupts
Table 6-19. External Interrupt Registers
NAME ADDRESS SIZE (×16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT2CR 0x00 7071 1 XINT2 configuration register
XINT3CR 0x00 7072 1 XINT3 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive
and negative edge. For more information, see the Systems Control and Interrupts chapter of the
TMS320x2806x Piccolo Technical Reference Manual (SPRUH18).
6.8.1.1 External Interrupt Electrical Data/Timing
(1) For an explanation of the input qualifier parameters, see Table 6-76.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-20. External Interrupt Timing Requirements
(1)
MIN MAX UNIT
t
w(INT)
(2)
Pulse duration, INT input low/high
Synchronous 1t
c(SCO)
cycles
With qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-76.
Table 6-21. External Interrupt Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(INT)
Delay time, INT low/high to interrupt-vector fetch t
w(IQSW)
+ 12t
c(SCO)
cycles
Figure 6-18. External Interrupt Timing