VIPA System 300S SPEED7 CPU 313SC/DPM - Page 68

Chapter 4 Deployment CPU 313SC/DPM Manual VIPA System 300S SPEED7
4-28 HB140E - CPU SC - RE_313-6CF03 - Rev. 07/45
The CPUs include security mechanisms like a Watchdog (100ms) and a
parameterizable cycle time surveillance (parameterizable min. 1ms) that
stop res. execute a RESET at the CPU in case of an error and set it into a
defined STOP state.
The VIPA CPUs are developed function secure and have the following
system properties:
Event concerns Effect
RUN → STOP
general
BASP (Befehls-Ausgabe-Sperre, i.e. command
output lock) is set.
central digital outputs The outputs are set to 0V.
central analog outputs The voltage supply for the output channels is
switched off.
decentralized outputs The outputs are set to 0V.
decentralized inputs The inputs are read constantly from the slave
and the recent values are put at disposal.
STOP → RUN
respectively
PowerON
general First the PII is deleted, then OB 100 is called.
After the execution of the OB, the BASP is reset
and the cycle starts with:
Delete PIQ → Read PII → OB 1.
central analog outputs The behavior of the outputs at restart can be
preset.
decentralized inputs The inputs are read constantly from the slave
and the recent values are put at disposal.
RUN general The program execution happens cyclically and
can therefore be foreseen:
Read PII → OB 1 → Write PIQ.
PII = Process image inputs
PIQ = Process image outputs
Function
security