A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CPU PCA SW Debug Port
(aka BDM Connector)
Test Points
1 - Visual History Buffer Flush Status (’823 output)
2 - Reset Output (’823 input)
3 - Ground
4 - BDM Clock (’823 input)
5 - Ground
6 - Visual History Buffer Flush Status (’823 output)
7 - Reset Input (’823 Output)
8 - BDM Data Input (’823 Input)
9 - Vcc
10 - BDM Data Output (’823 Output)
Main PCA Connectors
Jim Belesiu
Jim Belesiu
Mar 5, 1999
Mar 5, 1999
620005.dsn
5-39173 JAC 3/18/99 LPP
L. Phillips
Z. Psenicnik
J. Bello
3/19/99
3/19/99
3/19/99
B
Component change for
frequency modulation
5-39353 JJC 4/15/99 ZIP
Change Reset IC U3,
No Load C40
C 5-39830 LPP 6/24/99
REV
Description
ECN/ECO Init
Date Ckd
A Release to Production
620005
C
Atlas CPU Subsystem
C
16Thursday, June 24, 1999
Title
Size
Document Number
Rev
Date: Sheet of
Welch Allyn Inc.
Schematic:
Release For Production
Approved
Checked
Designed
Drawn
Initial Date
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DSDO
ADC-Clock
SPI-data-in
TA_n
NIBP-15mmHg
PC6
CLKOUT
SpO2-Tx
Main-Supply-On
FE-Data
DSDI
SCD
Video-Horizontal-Sync
SPI-clock
NIBP-PWM-ADC
SpO2-Rx
Spare-1
On-Standby-Key
Video-Clock-3
EKG-PWM-ADC
RS423-CTS
SPI-data-out
PA4
ETCO2-Rx
NIBP2-PW-ADC
Vbackup
NIBP-Valve
Spare-3
RD/WR_n
PA14
SPIMISO
Nurse-Call
Key-Latch
Main-Power-Sync
Spare-2
NIBP-Overpressure
SCL
Batt-ID
ETCO2-Tx
PB16
PC10
VFLS1
+3.3V_unfiltered
Recorder-Data
PC13
HRESET_n
Video-Vertical-Sync
Recorder-Data-Latch
Burst_n
TS_n
AC-On
RS423-Tx
Recorder-Strobe
PA7
SRESET_nVFLS0
HRESET
Rec-Paper-Out
NIBP-Data
PC12
PA6
SPISEL_n
LED-Latch
NIBP-Offset-DAC
Video-Data
SPIMOSI
DSCK
+3.3V_unfiltered
Speaker-Audio
Recorder-Motor-Step
FE-Clock
PA5
PA15
NIBP-Fault
RS423-Rx
Recorder-Clock
SPICLK
VDDH
TP75
1
TP77
1
TP60
1
TP61
1
TP78
1
TP62
1
TP59
1
TP64
1
TP63
1
TP70
1
TP65
1
TP69
1
TP66
1
TP76
1
TP58
1
TP68
1
TP71
1
JP8
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TP72
1
TP67
1
TP73
1
TP74
1
JP5
HEADER 5X2
12
34
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78
910
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