Welch Allyn Atlas - Page 5

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Attach GND and
VSSSYN at a
single point.
Place VSSSYN
on a split
plane beneath
the MPC823 PLL
section
Jim Belesiu
Jim Belesiu
Mar 5, 1999
Mar 5, 1999
620005.dsn
3/18/99
JAC5-39173 LPP
L. Phillips
Z. Psenicnik
J. Bello
3/19/99
3/19/99
3/19/99
B
frequency modulation
Component change for 5-39353 JJC 4/15/99 ZIP
Change Reset IC U3,
No Load C40
C 5-39830 LPP 6/24/99
620005
C
PowerPC MPC823 CPU
C
56Thursday, June 24, 1999
Title
Size
Document Number
Rev
Date: Sheet of
Welch Allyn Inc.
Schematic:
Release For Production
Approved
Checked
Designed
Drawn
Initial Date
REV
Description
ECN/ECO Init
Date Ckd
A Release to Production
BG_n
BB_n
IRQ_n2
TEA_n
A27
D[0:31]
BS_AB[0:3]
IP_B2
IRQ_n7
D18
D4 D0
A22 A14
A[6:31]
IRQ_n[0:7]
IP_B4
TA_n
D30 D22 D21
D7 D6 D1
A30 A18
IP_B5
BR_n
D31 D23 D20 D15 D11
D9 D8
A24 A21 A20 A19 A17
A8
IP_B6
BS_AB0
IRQ_n4
SPKROUT
D29
A12 A11
IRQ_n1 IRQ_n5
CS_n7
D13
GPL5 GPL3
IRQ_n6
CS_n6 CS_n5 A25
IP_B3
BS_AB2
TSIZ1
CS_n4
D26 D24 D16
A6
GPL[0:7]
GPL6 GPL4
D28
D5 D3 D2
A26
GPL7
TSIZ0
CS_n0 A31 A28 A23
A9
GPL2
BI_n
D27 D25 D10
A16 A15 A10
CS_n[0:7]
IP_B7
FRZ
IRQ_n3
CS_n1
D12
A7
TSIZ[0:1]
BS_AB3
IRQ_n0
CS_n3
D14
A29
IP_B[2:7]
GPL1 GPL0
BS_AB1
CS_n2
D19
TS_n
D17
A13
VIDEO0 VIDEO1 VIDEO2 VIDEO3 VIDEO4 VIDEO5 VIDEO6 VIDEO7
GND VSSSYN
VIDEO[0:7]
A[6:31]
TSIZ[0:1]
TEXP
PORESET_n
EXTCLK
Field
HSYNC
SPISEL_n
SPIMOSI
SPICLK
Video-Clock-3
XTAL
MODCK2
XFC
MODCK1EXTAL
HRESET_n
VSYNC
SRESET_n
CLKOUT
Blank
SPIMISO
RD/WR_n
I2CSCL
I2CSDA
CS_n[0:7]
IRQ_n[0:7]
BS_AB[0:3]
SMRXD2
PA7
SMTXD2
PA6
PA4
PA5
PA15
PA14
TXD2
RXD2
PB19
PB16
PB18
PB17
SDACK2_n
SDACK1_n
SMTXD1
SMRXD1
DREQ1_n
PC13
DREQ2_n
PC12
PC10
PC11
PC7
PC5
PC8
PC9
PC6
DSDO
TMS
TRST_n
VFLS0
VFLS1
DSCK
RSTCONF_n
DSDI
D[0:31]
GPL[0:7]
WAIT_B_n
ALE_B
IP_B[2:7]
Burst_n
TS_n
TA_n
TEA_n
BI_n
BR_n
BG_n
BB_n
SPKROUT
FRZ
PC4
VDDH
VDDL
KAPWR VDDSYN
MPC823
WKHPRQVWHU
U1
MPC823ZC
M13 N15 N16 M15 L13 M16 M14 L14 L15 L16 K14 K13 G13 K15 J15 J14 G14 H15 H13 H14 F14 K16 G16 H16 G15 F16 M1 L1 J2 J1 L2 H1 F1 E1 M2 K2 K3 K1 M4 M3 J3 J4 H2 K4 H3 G2 G3 F2 H4 L4 F3 G4 E4 L3 F4 E2 D2 E3 D12 A14 B14 A15 B16 D13 C14 B15
E5
E6
E7
E8
E9
E10
E11
E12
F5
F12
G5
G12
H5
H12
J5
J12
K5
K12
L5
L12
M5
M6
M7
M8
M9
M10
A7
G1
J16
T7
F6 F7 F8 F9 F10 F11 G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 B1 A3 A1 A2
M11
M12
L6 L7 L8 L9 L10 L11 B3 C5 B5 B4 A4 A5 B2 D1 A6 D5 T1 P4 T2 N5 R3 P5 T3 R4 R2 R1 P2 P3 N4
F15 E15 C13 B10 A13 D10 A12 C11 B12 D9 B7 C3 D4 D3 C2 A10 N3 N2 N1 B11 A11 C10 D16 E16 D15 F13 E13 C16 C15 D14 D11 B13 C12
T12 R12 R11 N12 P11 C4 B8 A8 C8 D7 A9 B9 C9 C7 D8 D6 B6
P16
R15
R14
R13
N10
T9
T8
P8
T6
R6
N14
P15
P14
T15
T14
P12
N11
T11
T10
R9
R7
P7
N7
R5
R16
T16
P13
T13
R10
P9
R8
N8
T5
N6
P6
T4
A16
C1
C6
E14
J13
N9 N13 P1 P10
A6 A7 A8 A9
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
CS0_n CS1_n CS2_n CS3_n CS4_n CS5_n
CS6_n / CE1_B_n CS7_n / CE2_B_n
VDDH1
VDDH2
VDDH3
VDDH4
VDDH5
VDDH6
VDDH7
VDDH8
VDDH9
VDDH10
VDDH11
VDDH12
VDDH13
VDDH14
VDDH17
VDDH18
VDDH19
VDDH20
VDDH21
VDDH22
VDDH23
VDDH24
VDDH25
VDDH26
VDDH27
VDDH28
VDDL1
VDDL2
VDDL3
VDDL4
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 VDDSYN KAPWR VSSSYN VSSSYN1
VDDH29
VDDH30
GND37 GND38 GND39 GND40 GND41 GND42 PORESET_n RSTCONF_n HRESET_n SRESET_n XTAL EXTAL XFC CLKOUT EXTCLK TEXP VD0 / LD1 / PD8 VD1 / LD2 / PD9 VD2 / LD3 / PD10 VD3 / LD4 / PD11 VD4 / LD5 / PD12 VD5 / LD6 / PD13 VD6 / LD7 / PD14 VD7 / LD8 / PD15 FIELD / LD0 / PD7 BLANK / LOE / LCD_AC / PD6 VSYNC / FRAME / PD5 HSYNC / LOAD / PD4 CLK-SHIFT / PD3
TSIZ0 / REG_n
TSIZ1
RD / WR_n
Burst_n
BDIP_n / GPL_B5_n
TS_n TA_n
TEA_n
BI_n
RSV_n / IRQ2_n
KR_n / IRQ4_n / RETRY / SPKROUT
DP0 / IRQ3_n DP1 / IRQ4_n DP2 / IRQ5_n DP3 / IRQ6_n
FRZ / IRQ6_n
IRQ7_n IRQ1_n IRQ0_n
BR_n
BB_n
BG_n
WE0_n / BS_AB0_n / IORD_n
WE1_n / BS_AB1_n / IOWR_n
WE2_n / BS_AB2_n / PCOE_n
WE3_n / BS_AB3_n / PCWE_n
GPL_A0_n / GPL_B0_n
GPL_A1_n / GPL_B1_n / OE_n
GPL_A2_n / GPL_B2_n / CS2_n GPL_A3_n / GPL_B3_n / CS3_n
UPWAITA / GPL_A4_n / AS_n
UPWAITB / GPL_B4_n
GPL_A5_n
TCK / DSCK TMS TDI / DSDI TDO / DSDO TRST_n WAIT_B_n ALE_B / DSCK / AT1 IP_B0 / IWP0 / VFLS0 IP_B1 / IWP1 / VFLS1 IP_B2 / IOIS16_B_n / AT2 IP_B3 / IWP2 / VF2 IP_B4 / LWP0 / VF0 IP_B5 / LWP1 / VF1 IP_B6 / DSDI / AT0 IP_B7 / PTR_n / AT3 OP2 / MODCK1 / STS_n OP3 / MODCK2 / DSDO
PA15 / USBRXD
PA14 / USBOE_n
PA13 / RXD2
PA12 / TXD2
PA9 / L1TXDA / SMRXD2
PA8 / L1RXDA / SMTXD2
PA7 / CLK1 / TIN1 / L1RCLKA / BRGO1
PA6 / CLK2 / TOUT1_n / TIN3
PA5 / CLK3 / TIN2 / L1TCLKA / BRGO2
PA4 / CLK4 / TOUT2_n / TIN4
PB31 / SPISEL_n / LCD_A
PB30 / SPICLK
PB29 / SPIMOSI
PB28 / SPIMISO
PB27 / I2CSDA / BRGO1
PB26 / I2CSCL / BRGO2
PB25 / SMTXD1
PB24 / SMRXD1
PB23 / SMSYN1_n / SDACK1_n
PB22 / SMSYN2_n / SDACK2_n
PB19 / L1ST1 / LCD_B
PB18 / RTS2_n / L1ST2
PB17 / L1ST3 / LCD_C
PB16 / L1RQA / L1ST4
PC15 / DREQ1_n / L1ST5
PC14 / DREQ2_n / RTS2_n / L1ST6
PC13 / L1ST7
PC12 / L1RQA / L1ST8
PC11 / USBRXP
PC10 / TGATE1_n / USBRXN
PC9 / CTS2_n
PC8 / CD2_n / TGATE1_n
PC7 / USBTXP
PC6 / USBTXN
PC5 / L1TSYNCA / SDACK1_n
PC4 / L1RSYNCA
NC1
NC2
NC3
NC4
NC5
NC6 NC7 NC8 NC9