Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 133
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property IOSTANDARD LVCMOS18 [get_ports "PHY_RESET_LS"]
set_property PACKAGE_PIN P25 [get_ports "SGMII_RX_N"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "SGMII_RX_N"]
set_property PACKAGE_PIN P24 [get_ports "SGMII_RX_P"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "SGMII_RX_P"]
set_property PACKAGE_PIN M24 [get_ports "SGMII_TX_N"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "SGMII_TX_N"]
set_property PACKAGE_PIN N24 [get_ports "SGMII_TX_P"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "SGMII_TX_P"]
set_property PACKAGE_PIN N26 [get_ports "SGMIICLK_N"]
set_property IOSTANDARD LVDS_25 [get_ports "SGMIICLK_N"]
set_property IOSTANDARD LVDS_25 [get_ports "SGMIICLK_P"]
set_property PACKAGE_PIN P26 [get_ports "SGMIICLK_P"]
#PCIE
set_property PACKAGE_PIN K22 [get_ports "PCIE_PERST_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS"]
set_property PACKAGE_PIN N23 [get_ports "PCIE_WAKE_B_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_WAKE_B_LS"
]
#QSPI
set_property PACKAGE_PIN G26 [get_ports "QSPI1_CS_B"]
set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_CS_B"]
set_property PACKAGE_PIN M20 [get_ports "QSPI1_IO0"]
set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_IO0"]
set_property PACKAGE_PIN L20 [get_ports "QSPI1_IO1"]
set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_IO1"]
set_property PACKAGE_PIN R21 [get_ports "QSPI1_IO2"]
set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_IO2"]
set_property PACKAGE_PIN R22 [get_ports "QSPI1_IO3"]
set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_IO3"]
#SDIO
set_property PACKAGE_PIN AM10 [get_ports "SDIO_CD_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_CD_FPGA"]
set_property PACKAGE_PIN AL10 [get_ports "SDIO_CLK_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_CLK_FPGA"]
set_property PACKAGE_PIN AD9 [get_ports "SDIO_CMD_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_CMD_FPGA"]
set_property PACKAGE_PIN AP9 [get_ports "SDIO_DATA0_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_DATA0_FPGA"]
set_property PACKAGE_PIN AN9 [get_ports "SDIO_DATA1_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_DATA1_FPGA"]
set_property PACKAGE_PIN AH9 [get_ports "SDIO_DATA2_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_DATA2_FPGA"]
set_property PACKAGE_PIN AH8 [get_ports "SDIO_DATA3_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "SDIO_DATA3_FPGA"]
#SFP
set_property PACKAGE_PIN K21 [get_ports "SFP0_LOS_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SFP0_LOS_LS"]
set_property PACKAGE_PIN AL8 [get_ports "SFP0_TX_DISABLE"]
set_property IOSTANDARD LVCMOS18 [get_ports "SFP0_TX_DISABLE"]
set_property PACKAGE_PIN AM9 [get_ports "SFP1_LOS_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SFP1_LOS_LS"]
set_property PACKAGE_PIN D28 [get_ports "SFP1_TX_DISABLE"]
set_property IOSTANDARD LVCMOS18 [get_ports "SFP1_TX_DISABLE"]
#SYSTEM CONTROLLER
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English