Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 134
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property PACKAGE_PIN AJ10 [get_ports "SYSCTLR_GPIO_5"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_5"]
set_property PACKAGE_PIN AG9 [get_ports "SYSCTLR_GPIO_6"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_6"]
set_property PACKAGE_PIN AF10 [get_ports "SYSCTLR_GPIO_7"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_7"]
#SYSMON
set_property PACKAGE_PIN E13 [get_ports "SYSMON_AD0_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD0_R_N"]
set_property PACKAGE_PIN F13 [get_ports "SYSMON_AD0_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD0_R_P"]
set_property PACKAGE_PIN H13 [get_ports "SYSMON_AD2_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD2_R_N"]
set_property PACKAGE_PIN J13 [get_ports "SYSMON_AD2_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD2_R_P"]
set_property PACKAGE_PIN B11 [get_ports "SYSMON_AD8_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD8_R_N"]
set_property PACKAGE_PIN C11 [get_ports "SYSMON_AD8_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD8_R_P"]
set_property PACKAGE_PIN T27 [get_ports "SYSMON_MUX_ADDR0_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_MUX_ADDR0_LS"]
set_property PACKAGE_PIN R27 [get_ports "SYSMON_MUX_ADDR1_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_MUX_ADDR1_LS"]
set_property PACKAGE_PIN N27 [get_ports "SYSMON_MUX_ADDR2_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_MUX_ADDR2_LS"]
set_property PACKAGE_PIN N21 [get_ports "SYSMON_SCL_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL_LS"]
set_property PACKAGE_PIN M21 [get_ports "SYSMON_SDA_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA_LS"]
#USB UART
set_property PACKAGE_PIN L23 [get_ports "USB_UART_CTS"]
set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_CTS"]
set_property PACKAGE_PIN K27 [get_ports "USB_UART_RTS"]
set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_RTS"]
set_property PACKAGE_PIN G25 [get_ports "USB_UART_RX"]
set_property IOSTANDARD LVMOS18 [get_ports "USB_UART_RX"]
set_property PACKAGE_PIN K26 [get_ports "USB_UART_TX"]
set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_TX"]
#FAN
set_property PACKAGE_PIN AJ9 [get_ports "SM_FAN_PWM"]
set_property IOSTANDARD LVCMOS18 [get_ports "SM_FAN_PWM"]
set_property PACKAGE_PIN AJ8 [get_ports "SM_FAN_TACH"]
set_property IOSTANDARD LVCMOS18 [get_ports "SM_FAN_TACH"]
#MAXIM CABLE
set_property PACKAGE_PIN AL9 [get_ports "MAXIM_CABLE_B_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "MAXIM_CABLE_B_FPGA"]
#PMBUS
set_property PACKAGE_PIN AK10 [get_ports "PMBUS_ALERT_FPGA"]
set_property IOSTANDARD LVCMOS18 [get_ports "PMBUS_ALERT_FPGA"]
#VADJ PGOOD
set_property PACKAGE_PIN M27 [get_ports "VADJ_1V8_PGOOD_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "VADJ_1V8_PGOOD_LS"]
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English