Xilinx SP605 - Page 30

30 www.xilinx.com SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Chapter 1: SP605 Evaluation Board
Table 1-10: GTP SMA Clock Connections
U1 FPGA Pin Schematic Net Name SMA Pin
C9 SMA_RX_N J35.1
D9 SMA_RX_P J34.1
A8 SMA_TX_N J33.1
B8 SMA_TX_P J32.1
D11 SMA_REFCLK_N J36.1
C11 SMA_REFCLK_P J37.1