Xilinx VC707 User Manual

VC707 Evaluation Board www.xilinx.com 33
UG885 (v1.4) May 12, 2014
Feature Descriptions
•Quad 113:
• MGTREFCLK0 - SGMII clock
• MGTREFCLK1 - SMA clock
• Contains 3 GTX transceivers with one each allocated to SMA, SGMII and SFP
• Contains 1 unused GTX transceiver
•Quad 114:
• MGTREFCLK0 - Si5324 jitter attenuator
• Contains 4 GTX transceivers for PCIe
® lanes 4–7
•Quad 115:
• MGTREFCLK1 - PCIe edge connector clock
• Contains 4 GTX transceivers for PCIe lanes 0–3
•Quad 116:
• MGTREFCLK0 - FMC2 HPC GBTCLK1
• Contains 4 GTX transceivers for FMC2 HPC (DP4 – DP7)
• • Quad 117:
• MGTREFCLK0 - FMC2 HPC GBTCLK0
• Contains 4 GTX transceivers for FMC2 HPC (DP0 – DP3)
•Quad 118:
• MGTREFCLK0 - FMC1 HPC GBTCLK1
• Contains 4 GTX transceivers for FMC1 HPC (DP4 – DP7)
•Quad 119:
• MGTREFCLK0 - FMC1 HPC GBTCLK0
• Contains 4 GTX transceivers for FMC1 HPC (DP0 – DP3)
Table 1-11 lists the GTX interface connections to the FPGA (U1).
Table 1-11: GTX Interface Connections for FPGA U1
Transceiver Bank Net Name Connections
MGT_BANK_113 GTXE2_CHANNEL_X1Y0 SMA
GTXE2_CHANNEL_X1Y1 SGMII
GTXE2_CHANNEL_X1Y2 SFP+
GTXE2_CHANNEL_X1Y3 NC
MGTREFCLK0 SGMII_CLK
MGTREFCLK1 SMA_MGT_REFCLK
MGT_BANK_114 GTXE2_CHANNEL_X1Y4 PCIe7
GTXE2_CHANNEL_X1Y5 PCIe6
GTXE2_CHANNEL_X1Y6 PCIe5
GTXE2_CHANNEL_X1Y7 PCIe4
MGTREFCLK0 Si5324
MGTREFCLK1 NC
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Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English