Xilinx VCU128 User Manual

Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
Schematic Net
Name
I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
D31 RLD3_72B_DQ26 SSTL12 A4 DQ26 U39
A31 RLD3_72B_DQ27 SSTL12 J4 DQ27 U39
B32 RLD3_72B_DQ28 SSTL12 K3 DQ28 U39
A33 RLD3_72B_DQ29 SSTL12 K1 DQ29 U39
B30 RLD3_72B_DQ30 SSTL12 L6 DQ30 U39
A30 RLD3_72B_DQ31 SSTL12 L4 DQ31 U39
C28 RLD3_72B_DQ32 SSTL12 L2 DQ32 U39
C29 RLD3_72B_DQ33 SSTL12 M5 DQ33 U39
A29 RLD3_72B_DQ34 SSTL12 M3 DQ34 U39
B28 RLD3_72B_DQ35 SSTL12 N6 DQ35 U39
G42 RLD3_72B_DQ36 SSTL12 D11 DQ0 U37
G41 RLD3_72B_DQ37 SSTL12 E10 DQ1 U37
H42 RLD3_72B_DQ38 SSTL12 C8 DQ2 U37
G40 RLD3_72B_DQ39 SSTL12 C10 DQ3 U37
H43 RLD3_72B_DQ40 SSTL12 C12 DQ4 U37
J42 RLD3_72B_DQ41 SSTL12 B9 DQ5 U37
H40 RLD3_72B_DQ42 SSTL12 B11 DQ6 U37
J40 RLD3_72B_DQ43 SSTL12 A8 DQ7 U37
J41 RLD3_72B_DQ44 SSTL12 A10 DQ8 U37
D44 RLD3_72B_DQ45 SSTL12 J10 DQ9 U37
F45 RLD3_72B_DQ46 SSTL12 K11 DQ10 U37
F44 RLD3_72B_DQ47 SSTL12 K13 DQ11 U37
D46 RLD3_72B_DQ48 SSTL12 L8 DQ12 U37
F46 RLD3_72B_DQ49 SSTL12 L10 DQ13 U37
E44 RLD3_72B_DQ50 SSTL12 L12 DQ14 U37
E46 RLD3_72B_DQ51 SSTL12 M9 DQ15 U37
G45 RLD3_72B_DQ52 SSTL12 M11 DQ16 U37
H45 RLD3_72B_DQ53 SSTL12 N8 DQ17 U37
B46 RLD3_72B_DQ54 SSTL12 D3 DQ18 U37
A46 RLD3_72B_DQ55 SSTL12 E4 DQ19 U37
C43 RLD3_72B_DQ56 SSTL12 C6 DQ20 U37
B45 RLD3_72B_DQ57 SSTL12 C4 DQ21 U37
A45 RLD3_72B_DQ58 SSTL12 C2 DQ22 U37
C45 RLD3_72B_DQ59 SSTL12 B5 DQ23 U37
C44 RLD3_72B_DQ60 SSTL12 B3 DQ24 U37
D42 RLD3_72B_DQ61 SSTL12 A6 DQ25 U37
A43 RLD3_72B_DQ62 SSTL12 A4 DQ26 U37
D40 RLD3_72B_DQ63 SSTL12 J4 DQ27 U37
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 26
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English