Xilinx VCU128 - Appendix B: Xilinx Constraints File; Overview

Appendix B
Xilinx Constraints File
Overview
The Xilinx
®
design constraints (XDC) le template for the VCU128 board provides for designs
targeng the VCU128 evaluaon board. Net names in the constraints listed correlate with net
names on the latest VCU128 evaluaon board schemac. Idenfy the appropriate pins and
replace the net names with the net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more informaon.
The FMCP connector J18 (HSCP) is connected to 1.8V (nominal) VADJ banks 70 and 71. Because
dierent FMC cards implement dierent circuitry, the FMC bank I/O standards must be uniquely
dened by each customer.
IMPORTANT
! See VCU128 board documentaon for the XDC le.
Appendix B: Xilinx Constraints File
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 94
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