Xilinx VCU128 User Manual

○ 1.2V 168-ball BGA
○ Up to RL3-1866
The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V
VTT terminaon voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear
regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled
with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The
connecons between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are
listed in the following table.
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75
FPGA (U1)
Pin
Schematic Net
Name
I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
K29 RLD3_72B_DQ0 SSTL12 D11 DQ0 U39
J30 RLD3_72B_DQ1 SSTL12 E10 DQ1 U39
K32 RLD3_72B_DQ2 SSTL12 C8 DQ2 U39
J31 RLD3_72B_DQ3 SSTL12 C10 DQ3 U39
L29 RLD3_72B_DQ4 SSTL12 C12 DQ4 U39
L31 RLD3_72B_DQ5 SSTL12 B9 DQ5 U39
L30 RLD3_72B_DQ6 SSTL12 B11 DQ6 U39
J32 RLD3_72B_DQ7 SSTL12 A8 DQ7 U39
K31 RLD3_72B_DQ8 SSTL12 A10 DQ8 U39
G30 RLD3_72B_DQ9 SSTL12 J10 DQ9 U39
H30 RLD3_72B_DQ10 SSTL12 K11 DQ10 U39
F31 RLD3_72B_DQ11 SSTL12 K13 DQ11 U39
G28 RLD3_72B_DQ12 SSTL12 L8 DQ12 U39
H29 RLD3_72B_DQ13 SSTL12 L10 DQ13 U39
G31 RLD3_72B_DQ14 SSTL12 L12 DQ14 U39
G32 RLD3_72B_DQ15 SSTL12 M9 DQ15 U39
H32 RLD3_72B_DQ16 SSTL12 M11 DQ16 U39
F28 RLD3_72B_DQ17 SSTL12 N8 DQ17 U39
E33 RLD3_72B_DQ18 SSTL12 D3 DQ18 U39
F29 RLD3_72B_DQ19 SSTL12 E4 DQ19 U39
E29 RLD3_72B_DQ20 SSTL12 C6 DQ20 U39
C32 RLD3_72B_DQ21 SSTL12 C4 DQ21 U39
F33 RLD3_72B_DQ22 SSTL12 C2 DQ22 U39
D30 RLD3_72B_DQ23 SSTL12 B5 DQ23 U39
D32 RLD3_72B_DQ24 SSTL12 B3 DQ24 U39
D29 RLD3_72B_DQ25 SSTL12 A6 DQ25 U39
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 25
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English