Xilinx VCU128 User Manual

Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75 (cont'd)
FPGA (U1)
Pin
Schematic Net
Name
I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
C40 RLD3_72B_DQ64 SSTL12 K3 DQ28 U37
A39 RLD3_72B_DQ65 SSTL12 K1 DQ29 U37
A41 RLD3_72B_DQ66 SSTL12 L6 DQ30 U37
B41 RLD3_72B_DQ67 SSTL12 L4 DQ31 U37
B40 RLD3_72B_DQ68 SSTL12 L2 DQ32 U37
D41 RLD3_72B_DQ69 SSTL12 M5 DQ33 U37
B42 RLD3_72B_DQ70 SSTL12 M3 DQ34 U37
E41 RLD3_72B_DQ71 SSTL12 N6 DQ35 U37
J29 RLD3_72B_DM0 SSTL12 B7 DM0 U39
A28 RLD3_72B_DM1 SSTL12 M7 DM1 U39
G43 RLD3_72B_DM2 SSTL12 B7 DM0 U37
A40 RLD3_72B_DM3 SSTL12 M7 DM1 U37
D39 RLD3_72B_A0 SSTL12 E2 A0 U37, U39
A38 RLD3_72B_A1 SSTL12 F5 A1 U37, U39
B38 RLD3_72B_A2 SSTL12 F4 A2 U37, U39
J34 RLD3_72B_A3 SSTL12 F9 A3 U37, U39
K34 RLD3_72B_A4 SSTL12 F10 A4 U37, U39
K37 RLD3_72B_A5 SSTL12 F12 A5 U37, U39
C38 RLD3_72B_A6 SSTL12 G3 A6 U37, U39
E36 RLD3_72B_A7 SSTL12 F1 A7 U37, U39
B35 RLD3_72B_A8 SSTL12 G11 A8 U37, U39
L35 RLD3_72B_A9 SSTL12 F13 A9 U37, U39
D34 RLD3_72B_A10 SSTL12 H13 A10 U37, U39
E39 RLD3_72B_A11 SSTL12 D1 A11 U37, U39
A35 RLD3_72B_A12 SSTL12 H11 A12 U37, U39
C35 RLD3_72B_A13 SSTL12 D13 A13 U37, U39
E37 RLD3_72B_A14 SSTL12 H3 A14 U37, U39
E38 RLD3_72B_A15 SSTL12 G2 A15 U37, U39
C37 RLD3_72B_A16 SSTL12 H4 A16 U37, U39
B36 RLD3_72B_A17 SSTL12 H10 A17 U37, U39
F34 RLD3_72B_A18 SSTL12 G12 A18 U37, U39
J37 RLD3_72B_A19 SSTL12 H1 A19 U37, U39
C39 RLD3_72B_A20 SSTL12 F2 NF_A20 U37, U39
C34 RLD3_72B_BA0 SSTL12 G9 BA0 U37, U39
B37 RLD3_72B_BA1 SSTL12 G5 BA1 U37, U39
A36 RLD3_72B_BA2 SSTL12 H8 BA2 U37, U39
D36 RLD3_72B_BA3 SSTL12 H6 BA3 U37, U39
D37 RLD3_72B_WE_B SSTL12 F6 WE_B U37, U39
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 27
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English