Xilinx VCU128 User Manual

Programmable QSFP3 Clock
[Figure 2, callout 15]
The VCU128 evaluaon board has a SI570 I2C programmable low-jier 3.3V LVDS dierenal
oscillator (U82) connected to FPGA U1 GTY bank 132 MGTREFCLK0 P/N pins Y42 and Y43
(series capacitor coupled), respecvely.
On power-up, the U82 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluaon board resets the QSFP3 clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency tolerance: 50 ppm
• 3.3V LVDS dierenal output
The programmable QSFP3 clock circuit is shown in the following gure.
Figure 15: QSFP3 Clock
X21965-111918
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 45
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English