Xilinx VCU128 User Manual

IMPORTANT! The TCA9548 U53 and U54 RESET_B pin 3 control signal IIC_MUX_RESET_B is
connected to the I2C0 bus TCA6416A U65 port expander (Addr 0x20) port P05 pin 9. The
IIC_MUX_RESET_B signal must be driven hi-Z or High to enable I2C bus transacons with the target
devices connected to U53 and U54.
Figure 25: I2C0 Bus Topology
TCA64 16A
P00
P01
P02
P03
P04
P05
P06
P07
P10
P16
P17
BANK 65
BE41/BP42
0X20
MAX6643-OT_B
MAX6643_FANFAIL_B
VCCINT_VCCBRAM_HOT_N
PMIC_INTR
SI5328_INT_ALM
ICC_MUX_RESET-B
GEM3_EXP_RESET_B
MAX6643_FULL_SPEED
FMC_HSPC_PRSNT_M2C_B
MAIN_PMBUS_ALERT_B
INA226_PMBUS_ALERT
U65
PCA9544A
INT0_B
SD0/SC0
INT1_B
SD1/SC1
INT2_B
SD2/SC2
INT3_B
SD3/SC3
SDA/
SCL
0X75
U55
INA226_PMBUS_ALERT
INA226_PMBUS_SDA/SCL
NC
NC
MAIN_PMBUS_ALERT_B
MAIN_PMBUS_SDA/SCL
NC
SYSMON_SDA/SCL
XCVU37P
U1
BANK 67
BL28/BM27
D11/A15
XC7Z010
BANK 501
U42
L/S
U58
L/S
U60
L/S
U49
TCA9548A
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC4
SD5/SC5
SD6/SC6
SD7/SC7
0X74
IIC-EEPROM-SDA/SCL
SI5328_SDA/SCL
NOT CONNECTED
QSFP1_SI570_SDA/SCL
U53
TCA9548A
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
SD4/SC4
SD5/SC5
SD6/SC6
SD7/SC7
SDA/
SCL
0X76
U54
SDA/
SCL
QSFP2_SI570_SDA/SCL
QSFP3_SI570_SDA/SCL
QSFP4_SI570_SDA/SCL
NOT CONNECTED
FMCP_HSPC_IIC_SDA/SCL
NOT CONNECTED
QSFP1_I2C_SDA/SCL
NOT CONNECTED
SYSMON_SDA/SCL
QSFP2_I2C_SDA/SCL
QSFP3_I2C_SDA/SCL
QSFP4_I2C_SDA/SCL
SYSMON_SDA/SCL
SDA/
SCL
I2C0_SDA/SCL
X21652-112918
I2C Bus Addresses
User applicaons that communicate with any of the I2C bus I2C0 downstream devices must rst
set up a path to the desired target device through the appropriate bus switch: I2C0 U55
PCA9544A, address 0x75 (0b111101); U53 TCA9548A, address 0x74 (0b1110100), or U54
TCA9548A, address 0x76 (0b111110), respecvely. The following table lists the address for
each bus.
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 73
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Xilinx VCU128 Specifications

General

Brand	Xilinx
Model	VCU128
Category	Motherboard
Language	English