Xilinx Virtex-6 FPGA Getting Started Guide

54 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Modifying the Virtex-6 FPGA Targeted Reference Design
To load the recompiled xaui driver, select Install from a list or specific location, and
click Next. Browse and choose
v6_pcie_10Gdma_ddr3_xaui_axi\compiled_drivers\xaui, and click Next.
The Xilinx XAUI driver is installed. Click Finish (Figure 49).
X-Ref Target - Figure 49
Figure 49: Load Xilinx XAUI Driver
UG664_79_052011

Xilinx Virtex-6 FPGA Specifications

General

Technology	40nm
Clock Data Recovery (CDR)	Integrated
Logic Cells	Up to 760, 000
I/O Pins	Up to 1200
Transceiver Features	Pre-emphasis, equalization
Transceiver Protocol Support	PCIe, SATA, Ethernet, CPRI, OBSAI, Serial RapidIO
Power Consumption	Varies by model and configuration
Transceiver Type	Multi-Gigabit Transceivers (RocketIO GTP/GTX)