Toc-3
IM 01F06F00-01EN
APPENDIX 5. INTEGRATOR (IT) BLOCK .......................................................A5-1
A5.1 Schematic Diagram of Integrator Block ..................................................... A5-1
A5.2 Input Process Section ................................................................................... A5-2
A5.2.1 Determining Input Value Statuses ...................................................A5-2
A5.2.2 Converting the Rate .........................................................................A5-2
A5.2.3 Converting Accumulation .................................................................A5-3
A5.2.4 Determining the Input Flow Direction...............................................A5-3
A5.3 Adder ............................................................................................................... A5-4
A5.3.1 Status of Value after Addition ...........................................................A5-4
A5.3.2 Addition ............................................................................................A5-4
A5.4 Integrator ........................................................................................................ A5-4
A5.5 Output Process .............................................................................................. A5-6
A5.5.1 Status Determination .......................................................................A5-6
A5.5.2 Determining the Output Value .......................................................... A5-7
A5.5.3 Mode Handling ................................................................................A5-8
A5.6 Reset ................................................................................................................ A5-8
A5.6.1 Reset Trigger....................................................................................A5-8
A5.6.2 Reset Timing ....................................................................................A5-8
A5.6.3 Reset Process ..................................................................................A5-9
A5.7 List of Integrator Block Parameters ........................................................... A5-10
APPENDIX 6. Enhanced ARITHMETIC (AR) BLOCK ...................................A6-1
A6.1 Schematic Diagram of Arithmetic Block ................................................... A6-1
A6.2 Input Section .................................................................................................. A6-2
A6.2.1 Main Inputs ......................................................................................A6-2
A6.2.2 Auxiliary Inputs ................................................................................A6-2
A6.2.3 INPUT_OPTS .................................................................................A6-3
A6.2.4 Relationship between the Main Inputs and PV ...............................A6-3
A6.3 Computation Section .................................................................................... A6-4
A6.3.1 Computing Equations .....................................................................A6-4
A6.3.2 Enhanced Computing Equations ....................................................A6-4
A6.3.3 Compensated Values ...................................................................... A6-5
A6.3.4 Average Calculation ........................................................................A6-5
A6.4 Output Section .............................................................................................. A6-5
A6.4.1 Mode Handling ................................................................................A6-6
A6.4.2 Status Handling ...............................................................................A6-6
A6.5 List of the Arithmetic Block Parameters ..................................................... A6-7
A6.6 Example of Connection ................................................................................. A6-9
A6.7 Setting Procedure of the Mass Flow Rate Calculation ............................ A6-10
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