ZiLOG System 8000 Hardware Reference Manual

HRM
Zilog
HRM
When a packet command is complete and the SMDC command
register CR:EI bit is set, the SMC interrupts the host. The
interrupt acknowledge vector is:
Interrupt Acknowledge Vector
15 14 13 12 11 10 9 8 7 .•. 0
: DRV: ending status : vector
NAME
IV:VEC
IV:ES
IV:DRV
Dispatch Table
BITS
0-7
8-13
14-15
CONTENTS
vector from CR
packet command ending status
drive number 0-3
The dispatch table provides the address and status of each
of four packets .. If fewer than four drives are present, the
dispatch table ~ntries corresponding to nonexistant drives
should be present.but set-to zero. The dispatch table may
not cross a 64 kilobyte boundry. Before the dispatch table
address is sent to the controller, all packet status entries
should be initialized to IDLE(O). All packets should also
be initialized to O.
4-30
Zilog
4-30

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English