ZiLOG System 8000 Hardware Reference Manual

HRM
Status Register
Zilog
HRM
15 14 13 12 11 10 9 8
7
6
5
4
3
2
o
: DRV :ES: ending status: NDT l 0 : 0 : 0 : 0 : IP : IUS I BZ
NAME
SR:BZ
SR:IUS
SR:IP
SR:NDT
SR:ES
SR:DRV
Self-test
BIT
o
2
3-6
7
8-13
14-15
MEANING
controller busy from CR:CMD
interrupt under service
interrupt pending
reserved
no dispatch table/interrupt vector
packet ST or self test code
drive number 0-3
On power-up or after a controller initialization (CR:INIT),
the controller will be busy (SR:BZ) until the self test rou-
tine and initialization are complete. If the setftest fails,
the SMDC will remain busy. The status register (SR:ES) may
contain one of the following error codes:
8: 2910 sequencer error
9: 2901 ALU error
A: internal memory error
The status register should be examined only after it has
been determined that the busy bit was not reset. The
self test takes ,less than a second when successful.
Power-Up
The SMDC's SR:NDT status bit will be on after power-up or
controller initialization (CR:INIT). This indicates that the
dispatch table address and interrupt vector have not yet
been sent by the host. The four bytes are sent with the CR
command. After each byte is sent, the controller will
briefly be busy (SR:BZ) while the byte is absorbed. The host
waits until SR:BZ goes to zero after sending each byte. The
read-packet-addresses command is then given. When all five
commands have been given, SR:NDT is reset.
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Zilog
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ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English