Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 16
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 3: Hardware Design
Figure 3-2 represents the architecture of the 8-channel RF-DAC (RF-DAC0 to RF-DAC7). The
Scatter Gather (SG) DMA is used to source the data from the PL DDR memory controller to
the DACs. The DMA sends this data to the stream MUX block, which is connected to each of
the DAC channel's stream data path. Based on the channel select line input (PS-GPIOs
routed through extended multiplexed I/Os (EMIOs)) of the stream pipe, the data gets
routed to the corresponding RF-DAC channel. (See GPIO Selection.) In case of continuous
replay from DDR, DMA constantly fetches the data and streaming mux switches the channel
based on the user selection of enabled channels. For sample storag
e and replay from BRAM
mode,
the functionality of the memory loopback system is elaborated upon in Memory
Loopback Details.
X-Ref Target - Figure 3-2
Figure 3-2: Datapath Implementation for 8-Channel RF-DAC
Stream MuxSG DMAPL DDR + MIG
Memory
Loopback 0
DAC0
Memory
Loopback 1
DAC1
Memory
Loopback 2
DAC2
Memory
Loopback 3
DAC3
Memory
Loopback 4
DAC4
Memory
Loopback 5
DAC5
Memory
Loopback 6
DAC6
Memory
Loopback 7
DAC7
512 bits x 300 MHz
256 bits x 300 MHz 256 bits x DAC CLK
AXI
AXI Streaming Interface
X21293-092118
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC