reactive voltage drop D V
L
on X
L1
line impedance leads the current by 90 degrees.
Voltage drop D
V
C
on series capacitor lags the fault current by 90 degrees. Note that
line impedance X
L1
could be divided into two parts: one between the IED point and the
capacitor and one between the capacitor and the fault position. The resulting voltage
V
M
in IED point is this way proportional to sum of voltage drops on partial
impedances between the IED point and the fault position F, as presented by
( )
M F L1 C
V I j X X= × -
EQUATION1995-ANSI V1 EN-US (Equation 57)
en06000605_ansi.vsd
~
21
XS
X
L1
IF
V
V
M
Source
Fault voltage
Pre -fault voltage
X
C
Source voltage
V’
M
With bypassed
capacitor
With inserted
capacitor
F
X
ANSI06000605 V1 EN-US
Figure 92: Voltage inversion on series compensated line
en06000606_ansi.vsd
I
F
V
S
V
’
M
=
xV
L
xV
S
I
F
x
V
L
V
S
x
V
C
V
M
xV
S
With bypassed
capacitor
With inserted
capacitor
ANSI06000606 V1 EN-US
Figure 93: Phasor diagrams of currents and voltages for the bypassed and
inserted series capacitor during voltage inversion
It is obvious that voltage V
M
will lead the fault current I
F
as long as X
L1
> X
C
. This
situation corresponds, from the directionality point of view, to fault conditions on line
1MRK 504 163-UUS A Section 8
Impedance protection
Transformer protection RET670 2.2 ANSI 215
Application manual
To Next Page
Loading...
