12 PCA-6751 Series User's Manual
1.5.6 Watchdog timer configuration (JP4)
An onboard watchdog timer reduces the chance of disruptions which
EMP (electro-magnetic pulse) interference can cause. This is an invalu-
able protective device for standalone or unmanned applications. Setup
involves two jumpers and running the control software. (Refer to
Appendix A.)
When the watchdog timer is enabled and the CPU shuts down, the
watchdog timer will automatically either reset the system or generate
an interrupt on IRQ 11, depending on the setting of jumper JP4, as
shown below:
Table 1-5: Watchdog timer system reset select (JP4)
*System reset IRQ11 interrupt
JP4
* default setting
1
1