5-12 Service Guide N5242-90001
Theory of Operation PNA Series Microwave Network Analyzers
Synthesized Source Group Operation N5242A
A19 Test Set Motherboard
The A19 test set motherboard serves these functions:
• to act as an interface between the A17 CPU board and the auxiliary rear panel
interconnects.
• to provide ALC signals to the A21 HMA26.5.
• to route control signals to the signal separation group. Refer to “Signal Separation
Group Operation” on page 5-16 for more information.
Rear Panel Interconnects
The A19 test set motherboard includes the following rear panel interconnects.
TEST SET I/O A DB-25 female connector that is used to control external test sets. The
external test set bus consists of 13 multiplexed address and data lines,
three control lines, and an open-collector interrupt line. Pin assignments
are listed in Table 5-3 on page 5-13.
Up to 16 test sets may be “daisy-chained” on the bus at one time.
The Test Set I/O is not compatible with 8753 network analyzer test sets.
HANDLER I/O A rectangular 36-pin, female connector providing four independent parallel
input/output ports, nine control signal lines, one ground, and a power
supply line. This connector has Type 2 output pin assignments as listed in
Table 5-4 on page 5-14.
All signals are TTL-compatible. Data input/output ports consist of two 8-bit
output ports (Port A and Port B) and two 4-bit bidirectional ports (Port C
and Port D).
Connector settings can be changed using SCPI and COM commands. The
settings are not accessible from the front panel.
PWR I/O A DB-9 female connector. Pin assignments are listed in Table 5-5 on
page 5-15.
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