6 Language Dictionary
96 Series N6700 User’s Guide
Status Subsystem
Status register programming lets you determine the operating
condition of the power system at any time. The power system has
three groups of status registers; Operation, Questionable, and
Standard Event. The Operation and Questionable status groups each
consist of the Condition, Enable, and Event registers as well as NTR
and PTR filters.
The Standard Event status group is also programmed using Common
commands. Common commands control additional status functions
such as the Service Request Enable and the Status Byte registers.
Operation Status Group
The Operation Status registers record signals that occur during
normal operation. As shown below, the group consists of a
Condition, PTR/NTR, Event, and Enable register. The outputs of the
Operation Status register group are logically-ORed into the
OPERation summary bit (7) of the Status Byte register.
Questionable Status Group
The Questionable Status registers record signals that indicate
abnormal operation. As shown below, the group consists of the same
register types as the Status Operation group. The outputs of the
Questionable Status group are logically-ORed into the QUEStionable
summary bit (3) of the Status Byte register.
Standard Event Status Group
The Standard Event registers are programmed by Common
commands. The Standard Event event register latches events relating
to communication status. It is a read-only register that is cleared
when read. The Standard Event enable register functions similarly to
the enable registers of the Operation and Questionable status groups.
Status Byte Register
This register summarizes the information from all other status
groups as defined in the IEEE 488.2 Standard Digital Interface for
Programmable Instrumentation.
MSS and RQS Bits
MSS is a real-time (unlatched) summary of all Status Byte register
bits that are enabled by the Service Request Enable register. MSS is
set whenever the power system has one or more reasons for
requesting service. *STB? reads the MSS in bit position 6 of the
response but does not clear any of the bits in the Status Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the power
system requests service, it sets the SRQ interrupt line true and
latches RQS into bit 6 of the Status Byte register. When the controller
To Next Page
Loading...
Need help?
General
