Alinx AXU2CGA - Page 10

ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual
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AXU2CGB PS side DDR4 SDRAM data pin assignment is the same as
AXU2CGA, additional data signal assignment is as follows:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
N23
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
M23
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
L23
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
K23
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
N26
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
N27
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
J26
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
J27
PS_DDR4_DQ32
PS_DDR_DQ32_504
T22
PS_DDR4_DQ33
PS_DDR_DQ33_504
R22
PS_DDR4_DQ34
PS_DDR_DQ34_504
P22
PS_DDR4_DQ35
PS_DDR_DQ35_504
N22
PS_DDR4_DQ36
PS_DDR_DQ36_504
T23
PS_DDR4_DQ37
PS_DDR_DQ37_504
P24
PS_DDR4_DQ38
PS_DDR_DQ38_504
R24
PS_DDR4_DQ39
PS_DDR_DQ39_504
N24
PS_DDR4_DQ40
PS_DDR_DQ40_504
H24
PS_DDR4_DQ41
PS_DDR_DQ41_504
J24
PS_DDR4_DQ42
PS_DDR_DQ42_504
M24
PS_DDR4_DQ43
PS_DDR_DQ43_504
K24
PS_DDR4_DQ44
PS_DDR_DQ44_504
J22
PS_DDR4_DQ45
PS_DDR_DQ45_504
H22
PS_DDR4_DQ46
PS_DDR_DQ46_504
K22
PS_DDR4_DQ47
PS_DDR_DQ47_504
L22
PS_DDR4_DQ48
PS_DDR_DQ48_504
M25
PS_DDR4_DQ49
PS_DDR_DQ49_504
M26
PS_DDR4_DQ50
PS_DDR_DQ50_504
L25
PS_DDR4_DQ51
PS_DDR_DQ51_504
L26
PS_DDR4_DQ52
PS_DDR_DQ52_504
K28
PS_DDR4_DQ53
PS_DDR_DQ53_504
L28
PS_DDR4_DQ54
PS_DDR_DQ54_504
M28
PS_DDR4_DQ55
PS_DDR_DQ55_504
N28