ARM DSTREAM-ST - Figure 1-1 Example Reset Circuit Logic

TRST
RESET
RST
RST
GndGnd
ARM
Processor
VDD
VDD
TAP RESET
SYSTEM RESET
Open-drain
reset devices
e.g. STM1001
To other
logic
VDD
VDD
nTRST
nSRST
Manual
reset
10K
10K
100R
100nF
Signals from JTAG connector
Figure 1-1 Example reset circuit logic
1 ARM
®
DSTREAM-ST system design guidelines
1.1 Reset signals
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