ARM DSTREAM-ST - Target Voltage Reference (VTREF) signals

Tri-StateStop Park
Tri-State Acknowledge Tri-State
Tri-StateStop Park
DataTri-State Acknowledge Data Tri-StateParity
Start
StartData Data Parity
T
ih
T
is
DSTREAM output to
SWDIO
DSTREAM output to
SWDCLK
Target output to SWDIO
DSTREAM output to
SWDIO
DSTREAM output to
SWDCLK
Target output to SWDIO
T
os
T
high
T
low
Write cycle
Read cycle
Figure 2-4 SWD timing diagrams
The DSTREAM-ST unit writes data to SWDIO on the falling edge of SWDCLK. The DSTREAM-ST
unit reads data from SWDIO on the rising edge of SWDCLK. The target writes data to SWDIO on the
rising edge of SWDCLK. The target reads data from SWDIO on the rising edge of SWDCLK.
The following table shows the timing requirements for the SWD:
Table 2-5 SWD timing requirements
Parameter Min Max Description
T
high
10ns 500μs SWDCLK HIGH period
T
low
10ns 500μs SWDCLK LOW period
T
os
-5ns 5ns SWDIO Output skew to falling edge SWDCLK
T
is
4ns - Input Setup time required between SWDIO and rising edge SWDCLK
T
ih
1ns - Input Hold time required between SWDIO and rising edge SWDCLK
2 ARM
®
DSTREAM-ST target interface connections
2.3 About Serial Wire Debug (SWD)
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