1.1 Reset signals
All ARM processors have a main processor reset that might be called nRESET, BnRES, or HRESET.
This is asserted by one or more of these conditions:
• Power on reset.
• Manual push-button reset.
• Remote reset from the debugger (using DSTREAM-ST).
• Watchdog circuit reset (if appropriate to the application).
Any ARM processor including the JTAG interface has a second reset input called nTRST (TAP Reset).
This resets the debug logic, the Test Access Port (TAP) controller, and the boundary scan cells. It is
activated by remote JTAG reset (from DSTREAM-ST).
Note
ARM strongly recommends that the nRESET and nTRST signals are separately available on the JTAG
connector. If the nRESET and nTRST signals are linked together, resetting the system also resets the
TAP controller. This means that:
• It is not possible to debug a system from reset, because any breakpoints previously set are lost.
• You might have to start the debug session from the beginning, because DSTREAM-ST might not
recover when the TAP controller state is changed.
DSTREAM-ST reset signals
The DSTREAM-ST unit has two reset signals connected to the debug target hardware, nTRST and
nSRST.
What the signals do:
• nTRST drives the JTAG nTRST signal on the ARM processor. It is an output that is activated
whenever the debug software has to re-initialize the debug interface in the target system.
• nSRST is a bidirectional signal that both drives and senses the system reset signal on the target. By
default, this output is driven LOW by the debugger to re-initialize the target system.
Note
It is expected that the assertion of the nSRST line by the DSTREAM-ST unit will cause a warm reset
of the target system. If the nSRST line triggers a power-on reset (POR), then the debug connection
might be lost.
The target hardware must pull the reset lines to their inactive state to assure normal operation when the
JTAG interface is disconnected. In the DSTREAM-ST unit, the strong pull-up/pull-down resistance is
approximately 33Ω, and the weak pull-up/pull-down resistance is approximately 4.7kΩ.
As it is possible to alter the drive strength for nTRST and nSRST, target assemblies with various
different reset configurations can be supported.
Example reset circuits
The diagram shows a typical reset circuit logic for the ARM reset signals and the DSTREAM-ST reset
signals.
1 ARM
®
DSTREAM-ST system design guidelines
1.1 Reset signals
ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 1-13
Non-Confidential
To Next Page
Loading...
