ARM DSTREAM-ST - Signal Requirements; Data Setup and Hold; Figure 4-2 Data Waveforms

4.3 Signal requirements
Use the information below to understand the data setup and hold requirements, and switching thresholds
for the ARM DSTREAM-ST unit.
Data setup and hold
The following figure and table show the setup and hold timing of the trace signals with respect to
TRACECLK.
DDR
TRACECLK
Tsl ThlThhTsh
DATA
Figure 4-2 Data waveforms
Table 4-1 Data setup and hold
Parameter DSTREAM-ST Description
Tsh (min) 0.75ns Data setup high
Thh (min) 0.75ns Data hold high
Tsl (min) 0.75ns Data setup low
Thl (min) 0.75ns Data hold low
Note
DSTREAM-ST supports DDR clocking mode. Data is output on each edge of the TRACECLK signal
and TRACECLK (max) <= 300MHz.
Switching thresholds
The DSTREAM-ST senses the target signaling reference voltage (VTRef) and automatically adjusts its
switching thresholds to VTRef/2. For example, on a 3.3V target system, the switching thresholds are set
to 1.65V.
4 Target board design for tracing with ARM
®
DSTREAM-ST
4.3 Signal requirements
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