1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-
Chips (SoC)
Use the information in this section to work with Application-Specific Integrated Circuits (ASIC) or
System-on-Chips (SoCs).
This section contains the following subsections:
• 1.2.1 ASICs containing multiple devices on page 1-15.
• 1.2.2 Boundary scan test vectors on page 1-16.
1.2.1 ASICs containing multiple devices
If your system contains multiple devices that each have a JTAG Test Access Port (TAP) controller, you
must serially chain them so that DSTREAM-ST can communicate with all of them simultaneously. The
chaining can either be within the ASIC, or externally.
Note
There is no support in DSTREAM-ST for multiplexing TCK, TMS, TDI, TDO, and RTCK between
several different processors.
TAP controllers serially chained within the ASIC
The JTAG standard originally described serially chaining multiple devices on a PCB. This concept can
be extended to serially chaining multiple TAP controllers within an ASIC, as shown in the following
figure:
TDI
TDI
TDO
TAP
Controller
TCK
nTRST
TMS
TDO
TDI
Second Tap Device
TDO
TCK
nTRST
TMS
TCK
nTRST
TMS
TAP
Controller
First Tap Device
Figure 1-2 TAP Controllers serially chained within an ASIC
This configuration does not increase the package pin count. It does increase JTAG propagation delays,
but this impact can be small if unaddressed TAP controllers are placed into bypass mode.
TAP controllers serially chained externally
You can use separate pins on the ASIC for each JTAG port, and serially chain them externally (for
example on the PCB). This configuration can simplify device testing, and gives the greatest flexibility on
the PCB. However, this is at the cost of many pins on the device package.
1 ARM
®
DSTREAM-ST system design guidelines
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips (SoC)
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