ARM DSTREAM-ST - Figure 5-4 Timing Diagram for the D-Type JTAG Synchronizer

The following figure shows a corresponding partial timing diagram, and how TCKFallingEn and
TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals
gates the RTCK and TDO signals so that they only change state at the edges of TCK.
CLK
TCKRisingEn
TCK
TCKFallingEn
RTCK
TAPC
State
TDO
Figure 5-4 Timing diagram for the D-type JTAG synchronizer
5 Reference
5.1 About adaptive clocking to synchronize the JTAG port
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