0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0 1 2 3 4 5 6
Target VTref (V)
Voh & Vi(th) (V)
Voutput high Level - Voh
Vinput threshold - Vi (th)
Figure 1-4 Target interface logic levels
DSTREAM-ST can adapt interface levels down to VTRef of 1.2V.
By default, the nTRST and nSRST signals are pulled-up by 4.7K resistors within DSTREAM-ST and
driven (strong) low during resets. This allows the reset signals to be driven by other open-drain devices
or switches on the target board. The polarity and high/low drive strengths can be configured within the
software.
The input and output characteristics of the DSTREAM-ST unit are compatible with logic levels from
TTL-compatible, or CMOS logic in target systems. When assessing compatibility with other logic
systems, the output impedance of all signals is approximately 50Ω.
1 ARM
®
DSTREAM-ST system design guidelines
1.3 Physical and electrical connection guidelines
ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 1-18
Non-Confidential
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