ARM DSTREAM-ST - Arm JTAG 20 connector

2.7 I/O diagrams for the DSTREAM-ST connectors
The diagrams show the pin I/O circuits for the debug and trace connectors on the DSTREAM-ST unit.
Diagram A - Input
The input circuit diagram is shown in the following figure:
33R
-
-
-
V REF/2
Figure 2-12 Input
Diagram B - Output
The output circuit diagram is shown in the following figure:
33R
Figure 2-13 Output
Diagram C - Input/Output
The input/output circuit diagram is shown in the following figure:
33R
-
-
-
V REF/2
Figure 2-14 Input/Output
Diagram D - Reset output
The reset output circuit diagram is shown in the following figure:
33R
4K7
Strong driver
Weak driver
Figure 2-15 Reset output
Diagram E - Reset output with feedback
The reset output with feedback circuit diagram is shown in the following figure:
33R
4K7
Strong driver
Weak driver
-
-
-
V REF/2
Figure 2-16 Reset output with feedback
2 ARM
®
DSTREAM-ST target interface connections
2.7 I/O diagrams for the DSTREAM-ST connectors
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