ARM DSTREAM-ST - Default Chapter; Table of Contents

Contents
ARM
®
DSTREAM-ST System and Interface Design
Reference Guide
Preface
About this book ..................................................... ..................................................... 10
Chapter 1 ARM
®
DSTREAM-ST system design guidelines
1.1 Reset signals ..................................................... ..................................................... 1-13
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips
(SoC) ........................................................... ........................................................... 1-15
1.3 Physical and electrical connection guidelines ............................ ............................ 1-17
Chapter 2 ARM
®
DSTREAM-ST target interface connections
2.1 About the ARM
®
JTAG 20 connector pinouts and interface signals ............ ............ 2-20
2.2 About the CoreSight
™
20 connector pinouts and interface signals .......................... 2-22
2.3 About Serial Wire Debug (SWD) ...................................... ...................................... 2-25
2.4 About trace signals .................................................................................................. 2-27
2.5 About JTAG port timing characteristics ................................. ................................. 2-28
2.6 About JTAG port buffering ........................................... ........................................... 2-30
2.7 I/O diagrams for the DSTREAM-ST connectors ...................................................... 2-34
2.8 Voltage domains of the DSTREAM-ST unit .............................. .............................. 2-36
2.9 Series termination .................................................................................................... 2-37
Chapter 3 ARM
®
DSTREAM-ST USER Input/Output (IO) connections
3.1 About the USER I/O connector pinouts ................................. ................................. 3-39
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