ARM DSTREAM-ST - Overview of high-speed design

nTRST
CLK
TCK
TDO
TMO
TDI
ASIC
nCLR
D
Q
D
Q
nCLR
RTCK
TDO
TCK
nTRST
CLK
TMS
TDI
Figure 5-1 Basic JTAG port synchronizer
The following figure shows a partial timing diagram for the basic JTAG synchronizer. The delay can be
reduced by clocking the flip-flops from opposite edges of the system clock, because the second flip-flop
only provides better immunity to metastability problems. Even a single flip-flop synchronizer never
completely misses TCK events, because RTCK is part of a feedback loop controlling TCK.
CLK
TCK
RTCK
Figure 5-2 Timing diagram for the Basic JTAG synchronizer
It is common for an ASIC design flow and its design rules to impose a restriction that all flip-flops in a
design are clocked by one edge of a single clock. To interface this to a JTAG port that is completely
asynchronous to the system, it is necessary to convert the JTAG TCK events into clock enables for this
single clock, and to ensure that the JTAG port cannot overrun this synchronization delay.
The following figure shows one possible implementation of this circuit.
CK
EN
IN
nRESET
TMS
CKEN
TAP Ctrl
State
Machine
OUT
Scan
Chain
CKEN
TCKFallingEn
TCKRisingEn
Shift En
D
Q
nCLR
D Q
nCLR
D Q
nCLR
D Q
TDO
TMS
CLK
nTRST
TCK
RTCK
TDI
Figure 5-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules
5 Reference
5.1 About adaptive clocking to synchronize the JTAG port
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