CoreSight
™
20 interface signals
Table 2-4 CoreSight 20 signals
Signal I/O Description
TDI Output The Test Data In pin provides serial data to the target during debugging. TDI can be pulled
HIGH on the target.
TDO Input The Test Data Out pin receives serial data from the target during debugging. You are advised to
series terminate TDO close to the target processor. TDO is typically pulled HIGH on the
target.
TMS Output The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target.
TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
TCK Output The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically
pulled HIGH on the target.
RTCK Input The Return Test Clock pin echoes the test clock signal back to DSTREAM-ST for use with
adaptive mode clocking. If RTCK is generated by the target processor, you are advised to
series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use.
nTRST Output The Test Reset pin resets the TAP controller of the processor to allow debugging to take place.
nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM-ST to
initiate a reset. The polarity and strength of nTRST is configurable.
nSRST Input/Output The System Reset pin fully resets the target. This signal can be initiated by DSTREAM-ST or
by the target board (which might be detected by DSTREAM-ST). nSRST is typically pulled
HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of
nSRST is configurable.
DBGRQ Output The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is
rarely used by current systems and is usually pulled LOW on the target.
DBGACK Input The Debug Acknowledge pin notifies DSTREAM-ST that a debug request has been received
and the target processor is now in debug state. DBGACK is rarely used by current systems and
is usually pulled LOW on the target.
SWDIO (SWD
mode)
Input/Output The Serial Wire Data I/O pin sends and receives serial data to and from the target during
debugging. You are advised to series terminate SWDIO close to the target processor.
Note
SWDIO signal is bidirectional and the functionality is shared with a unidirectional JTAG TMS
line. Ensure that there are no buffers preventing bidirectional communication functionality.
SWCLK (SWD
mode)
Output The Serial Wire Clock pin clocks data into and out of the target during debugging.
SWO (SWD mode) Input The Serial Wire Output pin provides trace data to DSTREAM-ST. You are advised to series
terminate SWO close to the target processor. SWO is configurable to be captured on pin 6 or
14.
TraceD[0-3] Input The Trace Data [0-3] pins provide DSTREAM-ST with TPIU continuous mode trace data from
the target. You are advised to series terminate these signals close to the target processor.
TRACECLK (Trace
mode)
Input The Trace Clock pin provides DSTREAM-ST with the clock signal necessary to sample the
trace data signals. You are advised to series terminate TRACECLK close to the target
processor.
2 ARM
®
DSTREAM-ST target interface connections
2.2 About the CoreSight
™
20 connector pinouts and interface signals
ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2-23
Non-Confidential
To Next Page
Loading...
