ARM DSTREAM-ST - Page 6

List of Figures
ARM
®
DSTREAM-ST System and Interface Design
Reference Guide
Figure 1-1 Example reset circuit logic ..................................................................................................... 1-14
Figure 1-2 TAP Controllers serially chained within an ASIC ................................................................... 1-15
Figure 1-3 Typical JTAG connection scheme .......................................................................................... 1-17
Figure 1-4 Target interface logic levels ................................................................................................... 1-18
Figure 2-1 ARM JTAG 20 connector pinout ............................................................................................ 2-20
Figure 2-2 CoreSight 20 connector pinout .............................................................................................. 2-22
Figure 2-3 Typical SWD connections ...................................................................................................... 2-25
Figure 2-4 SWD timing diagrams ............................................................................................................ 2-26
Figure 2-5 Clock waveforms ................................................................................................................... 2-27
Figure 2-6 JTAG port timing diagram ...................................................................................................... 2-28
Figure 2-7 JTAG connection without buffers ........................................................................................... 2-30
Figure 2-8 JTAG connection with TDO buffer ......................................................................................... 2-30
Figure 2-9 Daisy-chained JTAG connection without buffers ................................................................... 2-31
Figure 2-10 Daisy-chained JTAG connection with TCK buffers ................................................................ 2-32
Figure 2-11 JTAG connection with de-skewed buffers .............................................................................. 2-33
Figure 2-12 Input ....................................................................................................................................... 2-34
Figure 2-13 Output .................................................................................................................................... 2-34
Figure 2-14 Input/Output ........................................................................................................................... 2-34
Figure 2-15 Reset output .......................................................................................................................... 2-34
Figure 2-16 Reset output with feedback ................................................................................................... 2-34
Figure 2-17 VTRef input ............................................................................................................................ 2-35
Figure 2-18 VTRef input (decoupled) ........................................................................................................ 2-35
ARM 100893_0100_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 6
Non-Confidential