R/W Read/Write. The R/W Line allows the microprocessor to control the
direction of data transfer among system components. When the voltage
level is high the R/W line is reading from the Data Bus into the
microprocessor. When the voltage level is low it is commanding an
external device to write the present contents of the Data Bus into a
peripheral support chip or memory. All transitions on this line occur
during Phase 1, which allows control of data transfers during Phase
2.
RDY - Ready. The RDY input permits delay of execution of any machine
cycle during which the RDY line is held low. If the Ready (RDY) line
goes from high to low during a Write cycle the processor will execute
that cycle and will stop in the next Read cycle.
SYNC - Synchronzing Signal. The SYNC signal is an output signal
produced when the 6502 microprocessor is fetching an opcode. This
line goes high during Phase 1, and stays high for the remainder of
the cycle. If the RDY line is pulled low during Phase 1 of a SYNC
high cycle, single-step operation of the 6502 microprocessor can be
achieved.
SO - Set Overflow. The SO line is an output line that sets the
Overflow bit in the Status Register. The Overflow bit is set to a
logic one {high) on a high to low transition on this pin.
RES - Reset. The Reset line is used to initialize the microprocessor
during power-up. As the Power Supply is turned on the RES line is
held low, resetting internal registers. When the line goes high the
processor will delay six Phase 1 to Phase 2 cycles. After the RES
delay the processor will fetch instructions from memory locations
FFFC and FFFD.
NMI - Non-maskable Interrupt. The Non Maskable Interrupt (NMI) input
interrupts the processor after it has completed the instruction being
executed when the NMI line was pulled low. The NMI interrupt cannot
be masked by the processor to prevent recognition of this interrupt.
The processor will not detect another NMI until this line has gone
high and then back to low. The NMI signal must be low for at least
two clock cycles in order to be recognized. The following steps take
place when an NMI signal is recognized:
• The values in the Program Counter and the processor Status register
are pushed on the stack into three successive locations determined
by the value of the stack pointer when NMI is detected.
• Locations FFFA and FFFB will be read to vector the processor to a
subroutine to handle the interrupt.
• The Interrupt mask in the processor Status register is set to a
one, disallowing a maskable interrupt.
The microprocessor will be returned to its original condition upon
reading a RTI instruction in the interrupt handler subroutine.
4-6 System Service Manual
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