IRQ - Interrupt Request. The IRQ request input is similar to the NMI
signal. Unlike the NMI signal, the IRQ input can be controlled by bit
2 of the Program Status register, the interrupt mask bit {I). If the
flag bit I is a logic one, signals on the IRQ input will be
disregarded. The IRQ line is level-sensitive, not edge-sensitive. The
processor will be interrupted as long the flag bit I is low and IRQ
is low. The processor performs the same steps as an NMI operation,
with different locations for the vector address (FFFE and FFFF). The
processor will be returned to its original condition upon reading a
RTI instruction in the interrupt handler subroutine.
ANTIC and CTIA Integrated Circuits.
The primary function of the ANTIC integrated circuit is to fetch data
from memory, independent of the processor, for display on the video
screen. Direct Memory Access (DMA), is used by the ANTIC chip to
retreive data from memory. The ANTIC chip requests the use of the
Address Bus and the Data Bus by sending a HALT signal to the
microprocessor, causing the processor to become "Tri-State" during
the next computer cycle. The ANTIC then addresses and reads from
memory the data for placement on the video screen. Once initiated,
the DMA is completely and automatically controlled by the ANTIC chip
without need for further microprocessor intervention.
In addition to the display DMA, the ANTIC chip also generates DMA
addresses for the refresh (REF signal) of the system dynamic RAM
memory. The ANTIC chip steals cycles from the 6502 processor to do
memory refresh and fetch graphics data when needed. Each byte of data
fetched from memory requires one machine cycle. Memory refresh takes
nine cycles out of every video display line, unless pre-empted by a
high resolution graphics mode. Memory refresh continues during
vertical blank. Once memory refresh starts on a line, it occurs every
four cycles unless pre-empted by DMA.
Graphics data retreived from memory, via the ANTIC DMA process, is
routed to the CTIA graphics registers. A color-luminance register is
contained on the CTIA chip and as the serial graphic data passes
through the CTIA chip it is "impressed" with color and luminance
values contained in these registers, before being sent to the video
display. Priority is assigned to all objects by the CTIA chip before
the serial graphics data is sent to the video display.
4.3.2 Motherboard Console System (400)
The 400 Console Motherboard contains the POKEY chip (A101), the PIA
chip (A102), the ROM Personality chips (A103, A104, A105), the
Keyboard Key-In/Key-Out analog multiplexers, the Memory Map Decoder
(Z103), the controller jacks (J101 through J104), the CPU connector
jack (J110), and the Keyboard connector jack (J105). See Figures 4-4
and 4-5.
ATARI Personal Computers 4-7
POKEY Integrated Circuit
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