45
7598H–AVR–07/09
ATtiny25/45/85
8.10.2 Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
9. Interrupts
This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85.
For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”
on page 11.
9.1 Interrupt Vectors in ATtiny25/45/85
Table 9-1. Reset and Interrupt Vectors
Vector
No.
Program
Address Source Interrupt Definition
1 0x0000 RESET
External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset
2 0x0001 INT0 External Interrupt Request 0
3 0x0002 PCINT0 Pin Change Interrupt Request 0
4 0x0003 TIM1_COMPA Timer/Counter1 Compare Match A
5 0x0004 TIM1_OVF Timer/Counter1 Overflow
6 0x0005 TIM0_OVF Timer/Counter0 Overflow
7 0x0006 EE_RDY EEPROM Ready
8 0x0007 ANA_COMP Analog Comparator
9 0x0008 ADC ADC Conversion Complete
10 0x0009 TIM1_COMPB Timer/Counter1 Compare Match B
11 0x000A TIM0_COMPA Timer/Counter0 Compare Match A
12 0x000B TIM0_COMPB Timer/Counter0 Compare Match B
13 0x000C WDT Watchdog Time-out
14 0x000D USI_START USI START
15 0x000E USI_OVF USI Overflow
To Next Page
Loading...
Need help?
General
