140
7679H–CAN–08/08
AT90CAN32/64/128
13.11.6 Timer/Counter3 Control Register C – TCCR3C
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to zero
when TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the Waveform Genera-
tion unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.
Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value
present in the COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnC bits are always read as zero.
13.11.7 Timer/Counter1 – TCNT1H and TCNT1L
13.11.8 Timer/Counter3 – TCNT3H and TCNT3L
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 116.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit 76543210
FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
TCNT3[15:8] TCNT3H
TCNT3[7:0] TCNT3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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