139
7679H–CAN–08/08
AT90CAN32/64/128
This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
13-10 and Figure 13-11.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
13.11.5 Timer/Counter1 Control Register C – TCCR1C
Table 13-5. Clock Select Bit Description
CSn2 CSn1 CSn0 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
I/O
/1 (No prescaling)
010clk
I/O
/8 (From prescaler)
011clk
I/O
/64 (From prescaler)
100clk
I/O
/256 (From prescaler)
101clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge.
1 1 1 External clock source on Tn pin. Clock on rising edge.
Bit 76543210
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
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