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7679H–CAN–08/08
AT90CAN32/64/128
17.11.8 USART1 Control and Status Register C – UCSR1C
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be written
to zero when UCSRnC is written.
• Bit 6 – UMSELn: USARTn Mode Select
This bit selects between asynchronous and synchronous mode of operation.
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Bit 76543210
– UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPO1L UCSR1C
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value00000110
Table 17-4. UMSELn Bit Settings
UMSELn Mode
0 Asynchronous Operation
1 Synchronous Operation
Table 17-5. UPMn Bits Settings
UPMn1 UPMn0 Parity Mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 17-6. USBSn Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
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