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V
CC
rise. The RESET signal is activated again, without any delay, when V
CC
decreases below
the detection level.
Figure 7-2. MCU Start-up, RESET
Tied to V
CC
Figure 7-3. MCU Start-up, RESET Extended Externally
Note: If V
POR
or V
CCRR
parameter range can not be followed, an External Reset is required.
7.1.4 External Reset
An External Reset is generated by a low level on the RESET
pin. Reset pulses longer than the
minimum pulse width (see Table 7-1) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the MCU after
the Time-out period – t
TOUT
–
has expired.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
POR
CC
V
CCRR
V
CCRR
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
RST
V
POR
CC
V
CCRR
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