2. Working principle: the system switches DVD signal and external input signal through the control
of N3, N4 by
N5 (CD4052): CD4052 is a select switch, which selects is the three-path signals of external input
tuning signal, MIC signal and left/right channel audio signal. When the player is selecting the state of
playing disc, MIC signal can be gated. Through CS5340, MIC signal converts to digital signal, which
inputs to decode board for processing and then output from pin 217 (ASDATO) of Mt1389 to power
amplifier board. Note: the MIC signal through CS5340 does not pass through N4 (74HCT125).
N7 (CS5340): convert the analog signal sent out from CD4052 into digital signal for processing in
rear stage circuit.
N3, N4 (74HCT125): 74HCT125 is a gating IC with 4-channel in it, which can select the 4-path
signals. N3 carries out the gating for the 4-path signals of clock signal MCLK, audio signal SDATA0,
SDATA1, SDATA2.
N12 (TAS5508): after performing pulse width modulating processing to the 4-path digital audio
signals of SDA, SDATA0, SDATA1, SDATA2, 10-channel output produces: left/right channel output on
input/output board, headphone left/right channel output, front left/right channel output on power
amplifier board, surround left/right channel output, subwoofer channel and centre channel output.
N13, N14 (TAS5112): it is a high-performance amplifying IC, which modulates and amplifies the
front left/right channel, surround left/right channel, centre and subwoofer after being PWM modulated by
N12 (TAS5508).
M0, M1. When M0, M1 is 0, 1, through the selection of DVD signal bu system, N3B, N3C,
N3D, N4A, N4B, N4C of tri state gate buffer open, N3A and N4D close, 1389 sends the digital audio
signals SDA_LR, SDA_SLSR, SDA_SCW, SCLK, LRCK to 5508 directly for formatting, and the system
clock MCLK of power amplifier board is provided by 1389 through pin 6 of XP207, after being converted
by CS5340 AD , MIC signals are directly sent inside 1389 for processing, and overlapped to left/right
channel to output together after processing; when M0, M1 is 1, 0, through the selection of external input
signal (radio set and external audio input) by the system, N3B, N3C, N3D, N4A, N4B, N4C, N3A of tri
state gate buffer close, N4D opens, after being converted by CS5340 AD , external audio signals are
connected to SCLK, LRCK, SDA_AD and sent to 5508 for format conversion, and the system clock
MCLK of power amplifier board is generated by external crystal oscillation Y3.
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