Beckhoff CB3064 Series - Page 88

Chapter: BIOS Settings Chipset
page 88 Beckhoff New Automation Technology CB3064-xxxx
6.4.2.1 PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration │PCI Express Clock Gating │
│ │Enabled/Disable for each root │
│ PCI Express Clock Gating [Enabled] │port. │
│ Legacy IO Low Latency [Disabled] │ │
│ Peer Memory Write Enable [Disabled] │ │
│ Compliance Test Mode [Disabled] │ │
│ PCIe-USB Glitch W/A │ │
│► PCI Express Gen3 Eq Lanes │ │
│ │ │
│ PCIE Port 5 is assigned to LAN │ │
│ PCIE Port 6 is assigned to LAN2 │ │
│► PCI Express Root Port 9 │ │
│► PCI Express Root Port 10 │────────────────────────────────│
│► PCI Express Root Port 11 │→←: Select Screen │
│► PCI Express Root Port 12 │↑↓: Select Item │
│ │Enter: Select │
│ │+/-: Change Opt. │
│ │F1: General Help │
│ │F2: Previous Values │
│ │F3: Optimized Defaults │
│ │F4: Save & Exit │
│ │ESC: Exit │
│ │ │
│ │ │
│ │ │
│ │ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
 PCI Express Clock Gating
Options: Disabled / Enabled
 Peer Memory Write Enable
Options: Disabled / Enabled
 Compliance Test Mode
Options: Disabled / Enabled
 PCIe-USB Glitch W/A
Options: Disabled / Enabled
 PCI Express Gen3 Eq Lanes
Sub menu: see "PCI Express Gen3 Eq Lanes" (page 89)
 PCI Express Root Port X
Sub menu: see "PCI Express Root Port" (page 90)