Bosch BMP581 - Page 28

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Modifications reserved | Data subject to change
without notice Document number: BST-BMP581-DS004-02
Latched Mode. In latched mode, the INT pin is asserted as long as an interrupt condition is TRUE, and the interrupt
source is enabled in INT_SOURCE. Between two adjacent assertions if the INT pin, there is a minimum gap of
t
int_deassert
. Figure 6 shows the timing of latched mode.
The deassertion of the INT pin in latched mode depends is handled in the following way:
 FIFO interrupts will be de-asserted when the interrupt condition does not apply any more. There is no dependency
on the setting of INT_STATUS.
 The data ready interrupt will be de-assered after reading the INT_STATUS.
 The pressure out-of-range interrupt will be de-assered after reading the INT_STATUS. If the data ready interrupt is
asserted, a new measurement data becomes available, the INT pin will stay asserted. There is no de-assertion
phase.
Figure 6: INT pin timing in latched mode
Exceptions. In the following cases, the minimal pulse length and minimal gap between pulses may be violated:
 If the FIFO gets disabled or is flushed (see Chapter 3.6.4 "FIFO configuration changes" for a description of the
conditions that cause a FIFO flush), an asserted FIFO interrupt will be de-asserted immediately and the
corresponding bits in INT_STATUS will be cleared. This may cause a violation of t
int_pulse
or t
int_deassert
.
 If the conditons apply that would cause a FIFO flush, the behavior of an asserted out-of-range interrupt is the same
as for the FIFO interrupt desribed above: the asserted interrupt will be de-asserted immediately and the
corresponding bits in INT_STATUS will be cleared. This may cause a violation of t
int_pulse
or t
int_deassert
.
 If the host reconfigures the FIFO threshold while INT is asserted, INT will get de-asserted immediately and the
INT_STATUS.fifo_ths will get cleared. This may cause a violation of t
int_pulse
. If the new FIFO threshold condition still
holds true, INT will reassert after t
int_deassert
.
 If data ready and FIFO interrupts are used together, t
int_deassert
may be violated.
 t
int_deassert
can be violated if FIFO interrupts are enabled at the same time with the data ready or the out-of-range
interrupt. There is no violations when data ready and out-of-range interrupts are enabled at the same time.
 Latched/pulsed mode switch. Any change between latched/pulsed mode has to be applied while interrupt is
disabled. The following operations must be executed:
 Turn off all INT sources (INT_SOURCE -> 0x00)
 Read the INT_STATUS register to clear the status
 Set the desired mode in INT_CONFIG.int_mode
INT_STATUS. Independently of the int_mode setting, the interrupt status bit in INT_STATUS will not be cleared
automatically. The FIFO status will be cleared only when the interrupt condtion does not apply any more and the
INT_STATUS register has been read. The data ready and the out-of-range status will be cleared when the
INT_STATUS register has been read.